资格

• 应征条件

  【Requirements】
  Front-end design and verification of ASIC
  RTL design by VerilogHDL/VHDL
  Design and verification using a general-purpose bus AMBA(AXI/APB) and OCP
  Assertion-Based Verification
  【Welcome skills】
  Design and verification of ASIC built-in CPU
  Design and verification of high-speed interfaces such as PCI Express and USB
  Random verification using SystemVerilog
  Testbench building that was applied verification methodology(UVM)
  English skill(overseas business trip, meeting with overseas engineers)
  【Skill improvement】
  Advanced verification techniques such as coverage driven verification and Random verification
  Global business experience

• 英文

  Conversational Level

• 其他语言

  None